Electrically alterable read-only semiconductor memories may be constructed using floating gate field effect transistors as storage cells in the core. Each cell is read by directing a 5-volt signal thereto and sensing any resulting current flow in the cell. Current flow is affected by the presence of charge on the floating gate which charge is urged on or off the gate by a 20-volt programming pulse directed to the cell over the same program line used for the 5-volt signal.
When the program line is changed from 5 volts to 20 volts, the sudden increase can be injurious to the storage cell, especially those cells that utilize a very thin oxide layer through which charge is tunneled to the floating gate. Also, sudden increases may cause spurious programming of unselected storage cells. Consequently, good design practice involves restricting the program pulse rise time to about 600 microseconds, which is quite slow in comparison to device times in typical memories. Typically, the rise time constraint must be applied externally to the semiconductor chip. It would be desirable, however, to free a system designer from this restraint by controlling the rise time of the programming pulse internally, on the chip itself. My invention provides a circuit which permits such an on chip control of rise time.